Semiconductor devices having through-vias and methods for fabricating the same

ABSTRACT

Semiconductor devices having through-vias and methods for fabricating the same are described. The method may include forming a hole opened toward a top surface of a substrate and partially penetrating the substrate, forming a sacrificial layer partially filling the hole, forming a through-via in the hole partially filled with the sacrificial layer, forming a via-insulating layer between the through-via and the substrate, and exposing the through-via through a bottom surface of the substrate. Forming the sacrificial layer may include forming an insulating flowable layer on the substrate, and constricting the insulating flowable layer to form a solidified flowable layer.

CROSS-REFERENCE TO RELATED APPLICATION

This U.S. non-provisional patent application claims priority under 35U.S.C. §119 to Korean Patent Application No. 10-2012-0014363, filed onFeb. 13, 2012, the entirety of which is incorporated by referenceherein.

FIELD

The inventive concept relates to semiconductors and, more particularly,to semiconductor devices having through-vias and methods for fabricatingthe same.

BACKGROUND

Generally, a silicon oxide layer may be formed by a chemical vapordeposition (CVD) for electrical insulation between a through-silicon viaand a substrate. As a size of the through-silicon via becomes reduced,it may be required to reduce a thickness of an insulating layer formedon a sidewall of the through-silicon via. The insulating layer may alsobe formed under the through-silicon via. Securing high etch selectivitybetween the substrate and the insulating layer may be very important ina process that projects the through-silicon via by recessing a bottomsurface of the substrate. If the insulating layer is etched during theprocess of protruding the through-silicon via, the through-silicon viamay be exposed. The exposed portion of the through-silicon via may actas a contamination or particle source. As a result, errors in subsequentprocesses may occur. Thus, it may be desired to improve etching marginof the insulating layer in the process of protruding the through-siliconvia.

SUMMARY

Embodiments of the inventive concept may provide semiconductor devicescapable of improving etching margin of a through-via-insulating layer ina process of protruding a through-via and methods for fabricating thesame.

Embodiments of the inventive concept may also provide semiconductordevices capable of sufficiently securing electrical insulation between athrough-via and a substrate and methods for fabricating the same.

Embodiments of the inventive concept may also provide semiconductordevices capable of preventing, reducing, or minimizing process error soas to improve electrical reliability and yield and methods forfabricating the same.

According to some features of the inventive concept, a sacrificial layermay be formed under a through-via. According to other features of theinventive concept, the sacrificial layer may be formed by a flowablechemical vapor deposition method. According to still other features ofthe inventive concept, the sacrificial layer may further be formed underthe through-via by the flowable chemical vapor deposition method, suchthat it is possible to sufficiently secure an etching margin of aninsulating layer around the through-via.

In one aspect, a method for fabricating a semiconductor device mayinclude: forming a hole opened toward a top surface of a substrate, thehole partially penetrating the substrate; forming a sacrificial layerpartially filling the hole; forming a through-via in the hole partiallyfilled with the sacrificial layer; forming a via-insulating layerbetween the through-via and the substrate; and exposing the through-viathrough a bottom surface of the substrate. Forming the sacrificial layermay include: forming an insulating flowable layer on the substrate; andconstricting the insulating flowable layer to form a solidified flowablelayer.

In some embodiments, forming the via-insulating layer may include: afterforming the sacrificial layer, forming an insulating layer extendingalong a surface of the sacrificial layer and an inner sidewall of thehole.

In other embodiments, forming the via-insulating layer may include:before forming the sacrificial layer, forming a first insulating layerextending an inner surface of the hole.

In still other embodiments, forming the via-insulating layer may furtherinclude: after forming the sacrificial layer, forming a secondinsulating layer extending a surface of the sacrificial layer and aninner sidewall of the first insulating layer in the hole.

In yet other embodiments, forming the insulating flowable layer mayinclude: providing a silicon-contained compound and an oxidizing agenton the substrate; and condensing the silicon-contained compound and theoxidizing agent.

In yet still other embodiments, forming the solidified flowable layermay include: performing a plasma treatment or an annealing treatment onthe insulating flowable layer to convert the insulating flowable layerinto a constricted silicon oxide layer having a solid phase.

In yet still other embodiments, exposing the through-via may include:recessing the bottom surface of the substrate to expose a lower end ofthe through-via, the lower end of the through-via being surrounded bythe sacrificial layer; forming a lower insulating layer covering thesacrificial layer on the recessed bottom surface; and planarizing thelower insulating layer and the sacrificial layer to expose the lower endof the through-via.

In yet still other embodiments, exposing the through-via may include:recessing the bottom surface of the substrate to expose the sacrificiallayer without protruding the through-via; forming a lower insulatinglayer on the recessed bottom surface; and selectively removing thesacrificial layer and the via-insulating layer to expose a lower end ofthe through-via.

In yet still other embodiments, the method may further include: forminga barrier metal layer between the via-insulating layer and thethrough-via.

In yet still other embodiments, the method may further include at leastone of the following: forming an integrated circuit and a metalinterconnection electrically connected to the through-via on the topsurface of the substrate; forming an upper terminal connected to themetal interconnection and electrically connected to the through-via;and/or forming a lower electrode electrically connected to thethrough-via on the bottom surface of the substrate.

In another aspect, a semiconductor device may include: a substratehaving an active surface, a non-active surface, and a via-hole extendingfrom the active surface to the non-active surface; a through-viaprovided in the via-hole; a via-insulating layer extending along aninner sidewall of the via-hole and surrounding a sidewall of thethrough-via; a sacrificial layer extending along the inner sidewall ofthe via-hole from the via-insulating layer to the non-active surface ofthe substrate; a lower insulating layer covering the non-active surfaceof the substrate; and a terminal provided on the lower insulating layerand electrically connected to the through-via.

In some embodiments, the sacrificial layer may include a flowablechemical vapor deposition layer, and the via-insulating layer mayinclude a non-flowable chemical vapor deposition layer

In other embodiments, the through-via may include a lower end notreaching the non-active surface of the substrate. The terminal mayinclude a protruded portion that protrudes toward the via-hole and isconnected to the lower end of the through-via. The protruded portion maybe electrically insulated from the substrate by the sacrificial layer.

In still other embodiments, the sacrificial layer may have a thicknesssubstantially equal to that of the via-insulating layer, and theprotruded portion of the terminal may have a width substantially equalto a width of the lower end of the through-via.

In yet other embodiments, the sacrificial layer may have a secondthickness greater than that of the via insulating layer, and theprotruded portion of the terminal may have a width less than that of thelower end of the through-via.

In yet still other embodiments, the through-via may include a lower endthat protrudes outward from the non-active surface of the substrate. Thesacrificial layer may surround a sidewall of the lower end of thethrough-via.

BRIEF DESCRIPTION OF THE DRAWINGS

The inventive concept will become more apparent in view of the attacheddrawings and accompanying detailed description.

FIG. 1 is a cross-sectional view illustrating a semiconductor deviceaccording to embodiments of the inventive concept;

FIGS. 2A to 2D are cross-sectional views illustrating various examplesof an electrical connection part of a semiconductor device according toembodiments of the inventive concept;

FIG. 3 is a cross-sectional view illustrating a semiconductor packageincluding a semiconductor device of FIG. 1;

FIGS. 4A to 4H are cross-sectional views illustrating a method forfabricating a semiconductor device according to some embodiments of theinventive concept;

FIG. 4I is a cross-sectional view illustrating a modified example of thedevice of FIG. 4H;

FIGS. 4J to 4L are enlarged views of a portion of the device of FIG. 4I;

FIGS. 5A and 5B are cross-sectional views illustrating modified examplesof the device of FIG. 4D;

FIGS. 6A to 6H are cross-sectional views illustrating a method forfabricating a semiconductor device according to other embodiments of theinventive concept;

FIG. 7A and 7B are cross-sectional views illustrating process examplesof the device of FIG. 6B;

FIG. 8A is a schematic block diagram illustrating an example of memorycards including semiconductor devices according to embodiments of theinventive concept; and

FIG. 8B is a schematic block diagram illustrating an example ofinformation processing systems including semiconductor devices accordingto embodiments of the inventive concept.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The inventive concept will now be described more fully hereinafter withreference to the accompanying drawings, in which exemplary embodimentsof the inventive concept are shown. The advantages and features of theinventive concept and methods of achieving them will be apparent fromthe following exemplary embodiments that will be described in moredetail with reference to the accompanying drawings. It should be noted,however, that the inventive concept is not limited to the followingexemplary embodiments, and may be implemented in various forms.Accordingly, the exemplary embodiments are provided only to disclose theinventive concept and let those skilled in the art know the category ofthe inventive concept. In the drawings, embodiments of the inventiveconcept are not limited to the specific examples provided herein and areexaggerated for clarity.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to limit the invention. As usedherein, the singular terms “a,” “an” and “the” are intended to includethe plural forms as well, unless the context clearly indicatesotherwise. As used herein, the term “and/or” includes any and allcombinations of one or more of the associated listed items. It will beunderstood that when an element is referred to as being “connected” or“coupled” to another element, it may be directly connected or coupled tothe other element or intervening elements may be present.

Similarly, it will be understood that when an element such as a layer,region or substrate is referred to as being “on” another element, it canbe directly on the other element or intervening elements may be present.In contrast, the term “directly” means that there are no interveningelements. It will be further understood that the terms “comprises”,“comprising,”, “includes” and/or “including”, when used herein, specifythe presence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

Additionally, the embodiment in the detailed description will bedescribed with sectional views as ideal exemplary views of the inventiveconcept. Accordingly, shapes of the exemplary views may be modifiedaccording to manufacturing techniques and/or allowable errors.Therefore, the embodiments of the inventive concept are not limited tothe specific shape illustrated in the exemplary views, but may includeother shapes that may be created according to manufacturing processes.Areas exemplified in the drawings have general properties, and are usedto illustrate specific shapes of elements. Thus, this should not beconstrued as limited to the scope of the inventive concept.

It will be also understood that although the terms first, second, thirdetc. may be used herein to describe various elements, these elementsshould not be limited by these terms. These terms are only used todistinguish one element from another element. Thus, a first element insome embodiments could be termed a second element in other embodimentswithout departing from the teachings of the present invention. Exemplaryembodiments of aspects of the present inventive concept explained andillustrated herein include their complementary counterparts. The samereference numerals or the same reference designators denote the sameelements throughout the specification.

Moreover, exemplary embodiments are described herein with reference tocross-sectional illustrations and/or plane illustrations that areidealized exemplary illustrations. Accordingly, variations from theshapes of the illustrations as a result, for example, of manufacturingtechniques and/or tolerances, are to be expected. Thus, exemplaryembodiments should not be construed as limited to the shapes of regionsillustrated herein but are to include deviations in shapes that result,for example, from manufacturing. For example, an etching regionillustrated as a rectangle will, typically, have rounded or curvedfeatures. Thus, the regions illustrated in the figures are schematic innature and their shapes are not intended to illustrate the actual shapeof a region of a device and are not intended to limit the scope ofexample embodiments.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this inventive concept belongs. Itwill be further understood that terms, such as those defined in commonlyused dictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art andthis specification and will not be interpreted in an idealized or overlyformal sense unless expressly so defined herein.

FIG. 1 is a cross-sectional view illustrating a semiconductor deviceaccording to embodiments of the inventive concept.

Referring to FIG. 1, a semiconductor device 1 may include an electricalconnection part 10 that transmits an electrical signal. The electricalsignal may vertically pass through a substrate 100 via the electricalconnection part 10. The electrical connection part 10 may include athrough-via 120 substantially vertically penetrating the substrate 100.The through-via 120 may include a conductive layer, which fills avia-hole 101 vertically penetrating the substrate 100. Additionally, thethrough-via 120 may further include a barrier layer 124 surrounding theconductive layer. A via-insulating layer 112 may be disposed on asidewall of the via-hole 101. The via-insulating layer 112 electricallyisolates the through-via 120 from the substrate 100. The semiconductordevice 1 may further include at least one of an upper terminal 108 and alower terminal 118. The upper terminal 108 may be disposed on an activesurface 100 a of the substrate 100 and be electrically connected to thethrough-via 120. The lower terminal 118 may be disposed on a non-activesurface 100 c of the substrate 100 and be electrically connected to thethrough-via 120. The upper terminal 108 and the lower terminal 118 mayinclude a solder ball, a solder bump, a re-interconnection, and/or pad.In some embodiments, the upper terminal 108 may include a solder balland the lower terminal 118 may include a pad. However, the inventiveconcept is not limited thereto.

An integrated circuit 103, a metal interconnection 152, and aninterlayer insulating layer 102 may be disposed on the active surface100 a of the substrate 100. The metal interconnection 152 may beelectrically connected to the integrated circuit 103 and have asingle-layered structure or a multi-layered structure. The interlayerinsulating layer 102 may cover the integrated circuit 103 and the metalinterconnection 152. An upper insulating layer 107 may be disposed onthe interlayer insulating layer 102. The upper insulating layer 107 mayopen a bonding pad 154 connected to the upper terminal 108. The metalinterconnection 152 may be electrically connected to the through-via120, such that the integrated circuit 103 may be electrically connectedto the through-via 120. The through-via 120 may be disposed around theintegrated circuit 103 or in the integrated circuit 103. The electricalconnection part 10 may include one of the connection parts 11, 12, 13,and 14 of various structures as described with reference to FIGS. 2A to2D below. A lower insulating layer 109 may be disposed on the non-activesurface 100 c. The lower insulating layer 109 may open the through-via120 to which the lower terminal 118 is connected.

<Examples of Electrical Connection Part>

FIGS. 2A to 2D are cross-sectional views illustrating various examplesof an electrical connection part of a semiconductor device according toembodiments of the inventive concept.

Referring to FIG. 2A, the electrical connection part 11 may have avia-middle structure. In the via-middle structure, the through-via 120may be formed after the formation of the integrated circuit 103 andbefore the formation of the metal interconnection 152. The interlayerinsulating layer 102 may include a first interlayer insulating layer 104and a second interlayer insulating layer 106. The first interlayerinsulating layer 104 may be formed on the active surface 100 a of thesubstrate 100 and cover the integrated circuit 103. The secondinterlayer insulating layer 106 may be formed on the first interlayerinsulating layer 104 and cover the metal interconnection 142 and thebonding pad 154. The through-via 120 may successively penetrate thefirst interlayer insulating layer 104 and the substrate 100. Thethrough-via 120 may protrude outward from the non-active surface 100 cof the substrate 100. A sidewall of the protruded lower end 120 b of thethrough-via 120 may be surrounded by the via-insulating layer 112. Thevia-insulating layer 112 may be a chemical vapor deposition (CVD) layer.

In a modified example of the present example, as illustrated in FIG. 4I,an electrical connection part 11 a may further include a tail 110 tsurrounding the sidewall of the lower end 120 b of the through-via 120.In this case, as illustrated in FIG. 4J, the sidewall of the lower end120 b of the through-via 120 may be directly in contact with thevia-insulating layer 112, and the tail 110 t may surround thevia-insulating layer 112. Thus, the via-insulating layer 112 and thetail 110 t may constitute a double layer structure to suppress a contactof the substrate 100 and the sidewall of the lower end 120 b of thethrough-via 120 adjacent to the non-active surface 100 c of thesubstrate 100. The tail 110 t may be a portion of sacrificial layer (110of FIG. 4B) formed of a flowable chemical vapor deposition (FCVD) layer.In other embodiments, as illustrated in FIG. 4K, the sidewall of thelower end 120 b of the through-via 120 may be directly in contact withthe tail 110 t, and the via-insulating layer 112 may surround the tail110 t. In still other embodiments, as illustrated in FIG. 4L, a secondvia-insulating layer 113 may be further provided between the through-via120 and the via-insulating layer 112. In this case, the sidewall of thelower end 120 b of the through-via 120 may be directly in contact withthe second via-insulating layer 113, and the tail 110 t and thevia-insulating layer 112 may surround the second via-insulating layer113 in contact with the sidewall of the lower end 120 b of thethrough-via 120.

Referring to FIG. 2B, the electrical connection part 12 may have avia-last structure. In the via-last structure, the through-via 120 maybe formed after the integrated circuit 103 and the metal interconnection152 are sequentially formed. The through-via 120 may successivelypenetrate the second interlayer insulating layer 106, the firstinterlayer insulating layer 104, and the substrate 100. An upperinterconnection 153 may further be formed on the upper insulating layer107. The upper interconnection 153 may electrically connect thethrough-via 120 and the bonding pad 154 to each other. The through-via120 may further penetrate the upper insulating layer 107 to be connectedto the upper interconnection 153. The upper terminal 108 may beconnected to the bonding pad 154 through the upper interconnection 153,such that the upper terminal 108 may be electrically connected to themetal interconnection 152. The tail 110 t may be provided to surroundthe sidewall of the lower end 120 b of the through-via 120. In otherembodiments, the tail 110 t may be omitted.

Referring to FIG. 2C, the electrical connection part 13 may have avia-first structure. In the via-first structure, after the through-via120 is formed to penetrate the substrate 100, the integrated circuit 103and the metal interconnection 152 may be sequentially formed. Aconnecting interconnection 156 may further be formed on the activesurface 100 a of the substrate 100 with an insulating layer 133therebetween. The connecting interconnection 156 may be electricallyconnected to the through-via 120. The through-via 120 may beelectrically connected to the metal interconnection 152 and/or theintegrated circuit 103 through a via 158 connecting the connectinginterconnection 156 and the metal interconnection 152 to each other. Thetail 100 t may be provided to surround the sidewall of the lower end 120b of the through-via 120. In other embodiments, the tail 110 t may beomitted.

Referring to FIG. 2D, the electrical connection part 14 may include thethrough-via 120 recessed with respect to the non-active surface 100 c ofthe substrate 100. For example, the lower end 120 b of the through-via120 may be disposed at a level higher than the non-active surface 100 cof the substrate 100. The lower terminal 118 may include a portion thatprotrudes toward the lower end 120 b of the through-via 120. Theelectrical connection part 14 may include the via-insulating layer 112extending along a sidewall of the through-via 120 to the lower end 120 bof the through-via 120 or to a level lower than the lower end 120 b.Additionally, the electrical connection part 14 may further include asacrificial layer 110 b extending from the via-insulating layer 112 tothe non-active surface 100 c of the substrate 100. The via-insulatinglayer 112 may electrically insulate the through-via 120 from thesubstrate 100, and the sacrificial layer 110 b may electrically insulatethe lower terminal 118 from the substrate 100. The sacrificial layer 110b may be a flowable CVD layer. The via-insulating layer 112 may have athickness equal to, similar to, or different from that of thesacrificial layer 110 b. This will be described in more detail withreference to FIGS. 6E to 6G. The electrical connection part 14 mayinclude the via-middle structure, the via-last structure of FIG. 2B or2C, or the via-first structure.

<Example of Semiconductor Package>

FIG. 3 is a cross-sectional view illustrating a semiconductor packageincluding a semiconductor device of FIG. 1.

Referring to FIG. 3, a semiconductor package 90 may include a packagesubstrate 80 and one or more semiconductor devices 1 of FIG. 1 mountedon the package substrate 80. The semiconductor package 90 may furtherinclude a molding layer 80 molding the semiconductor devices 1. Thepackage substrate 80 may include a top surface 80 a and a bottom surface80 b opposite to the top surface 80 a. The package substrate 80 may be aprinted circuit board (PCB) within which electrical connectinginterconnections 82 are included. The semiconductor devices 1 may bemounted on the top surface 80 a of the package substrate 80 in a facedown state, such that active surfaces 100 a of the semiconductor devices1 face the package substrate 80. The semiconductor package 90 mayfurther include one or more solder balls 84, which are adhered on thebottom surface 80 b of the package substrate 80 and are connected to theelectrical connecting interconnection 82. In the present embodiment, theelectrical connections between the semiconductor devices 1 and betweenthe semiconductor devices 1 and the package substrate 80 may be realizedby the through-vias 120. The electrical connection parts 10 of thesemiconductor devices 1 may be replaced with one of the electricalconnection parts 11 to 14 illustrated in FIGS. 2A to 2D.

<Embodiment of Fabricating Method>

FIGS. 4A to 4H are cross-sectional views illustrating a method forfabricating a semiconductor device according to some embodiments of theinventive concept. FIG. 4I is a cross-sectional view illustrating amodified example of the device of FIG. 4H. FIGS. 4J to 4L are enlargedviews of a portion of FIG. 4I. FIGS. 5A and 5B are cross-sectional viewsillustrating modified examples of the device of FIG. 4D.

Referring to FIG. 4A, a via-hole 101 may be formed to substantiallyvertically penetrate a substrate 100. The substrate 100 may include atop surface 100 a and a first bottom surface 100 b opposite to the topsurface 100 a. An integrated circuit 103 may be formed on the topsurface 100 a of the substrate 100. A first interlayer insulating layer104 covering the integrated circuit 103 may be formed on the top surface100 a of the substrate 100. The substrate 100 may be a silicon substrateincluding a semiconductor material, such as silicon. The integratedcircuit 103 may include a memory circuit, a logic circuit, orcombination thereof. The first interlayer insulating layer 104 may beformed by depositing a silicon oxide layer or a silicon nitride layer.The via-hole 101 may substantially vertically penetrate the firstinterlayer insulating layer 104 and the substrate 100. The via-hole 101may be opened toward the top surface 100 a and have a depth not reachingthe first bottom surface 100 b. The via-hole 101 may be formed aroundthe integrated circuit 103, for example, a scribe lane or a regionadjacent thereto. The via-hole 101 may be formed in a hollowpillar-shape by an etching process or a drilling process. Alternatively,the via-hole 101 may be formed in a region in which the integratedcircuit 103 is formed.

Referring to FIG. 4B, a sacrificial layer 110 may be formed to partiallyfill the via-hole 101. For example, an insulator may be deposited usinga spin coating method, a spray coating method, a spin-on-glass (SOG)method, or a flowable chemical vapor deposition (FCVD) method, so thatthe sacrificial layer 110 may be formed in the via-hole 101. In thepresent embodiment, the sacrificial layer 110 may be formed using theFCVD method. The FCVD method may include providing a silicon-containedcompound (e.g., organo-silane and/or organo-siloxane) and an oxidizingagent (e.g., ethanol and/or isopropyl alcohol) on the substrate 100,condensing the silicon-contained compound and the oxidizing agent todeposit a flowable layer having Si—O, Si—H, and/or Si—OH combination,and converting the flowable layer to a solid phase silicon oxide layer(e.g., SiO₂).

Depositing the flowable layer may be performed at a low temperature(e.g., about −20 degrees Celsius to about 100 degrees Celsius, or about20 degrees Celsius to about 100 degrees Celsius) under a low pressure(e.g., about 1 Torr to about 100 Torr) without plasma. Converting theflowable layer to the silicon oxide layer may be performed in a plasmaenvironment (e.g., oxygen, helium, and/or argon plasma) or annealingtreatment of a temperature of about 200 degrees Celsius and a lowpressure (e.g., less than about 10 Torr). Thus, the flowable layer maybe solidified and be constricted to be formed into the silicon oxidelayer. A thickness or a shape filling the via-hole 101 of thesacrificial layer 110 may be varied according to the process condition.For example, the sacrificial layer 110 may include a tail 110 textending along a sidewall of the via-hole toward the top surface 100 aaccording to flowable characteristic of the flowable layer, which may begenerated by the condition of the FCVD process. Alternatively, thesacrificial layer 110 may not include the tail 110 t.

Referring to FIG. 4C, an insulating layer 112 a may be formed in thevia-hole 110 partially filled with the sacrificial layer 110 and then aconductive layer 120 a may be formed on the insulating layer 112 a.Additionally, a metal layer 124 a may further be formed before theconductive layer 120 a is formed. The insulating layer 112 a may beformed by depositing a silicon oxide layer or a silicon nitride layer ona surface of the sacrificial layer 110 and an inner sidewall of thevia-hole 101. The deposition for the formation of the insulating layer112 a may use a chemical vapor deposition, for example, aplasma-enhanced chemical vapor deposition (PECVD). If the conductivelayer 120 a includes copper (Cu), the metal layer 124 a may include ametal capable of preventing or reducing diffusion of copper. Forexample, the metal layer 124 a may be formed by depositing titanium(Ti), chromium (Cr), tantalum (Ta), nickel (Ni), or any combinationthereof. The conductive layer 120 a may be formed of silicon, copper,tungsten, and/or aluminum by a deposition method or a plating method. Ifthe conductive layer 120 a is formed using the plating method, a seedlayer may further be formed on the insulating layer 112 a. If the metallayer 124 a is formed, the seed layer may be formed on the metal layer124 a.

Referring to FIG. 4D, the conductive layer 120 a and the insulatinglayer 112 a may be planarized to expose the first interlayer insulatinglayer 104. The planarization process may be performed by an etch-backprocess or a chemical mechanical polishing (CMP) process. Due to theplanarization process, the conductive layer 120 a may be formed into athrough-via 120 vertically penetrating the first interlayer insulatinglayer 104 and the substrate 100, and the insulating layer 112 a may beformed into a via-insulating layer 112 electrically insulating thethrough-via 120 from the substrate 100. If the metal layer 124 a isfurther formed, due to the planarization process, the metal layer 124 amay be formed into the barrier layer 124 of FIG. 2A. The barrier layer124 may prevent or reduce the likelihood of an element (e.g., copper) ofthe through-via 120 from being diffused into the substrate 100 or theintegrated circuit 103.

In other embodiments, as illustrated in FIG. 5A, after thevia-insulating layer 112 is formed to extend along the inner surface ofthe via-hole 101, the sacrificial layer 110 may be formed to fill alower part of the via-hole 101. And then the through-via 120 may beformed to fill the rest part of the via-hole 101. In still otherembodiments, as illustrated in FIG. 5B, after the via-insulating layer112 is formed to extend along the inner surface of the via-hole 101 andthe sacrificial layer is formed to fill the lower part of the via-hole101, a second via-insulating layer 113 may further be formed. And thenthe through-via 120 may be formed to fill the via-hole 101. The secondvia-insulating layer 113 may be formed to extend along the surface ofthe sacrificial layer 110 and an inner sidewall of the via-insulatinglayer 112 by the same process as or a similar process to the process forthe formation of the via-insulating layer 112.

Referring to FIG. 4E, a back-end process may be performed. In someembodiments, a metal interconnection 152, a bonding pad 154, and asecond interlayer insulating layer 106 may be formed on the firstinterlayer insulating layer 104. The metal interconnection 152 may beconnected to the through-via 120 and have a single-layered structure ora multi-layered structure. The bonding pad 154 may be electricallyconnected to the metal interconnection 152. The second interlayerinsulating layer 106 may cover the metal interconnection 152 and thebonding pad 154. The metal interconnection 152 and the bonding pad 154may be formed by depositing a metal, such as copper or aluminum, andpatterning the metal. The second interlayer insulating layer 106 may beformed by depositing the same insulator as or a similar insulator to thefirst interlayer insulating layer 104, for example, a silicon oxidelayer or a silicon nitride layer. An upper insulating layer 107 may beformed on the second interlayer insulating layer 106. The upperinsulating layer 107 may be formed by depositing a silicon oxide layer,a silicon nitride layer, or a polymer. The upper insulating layer 107may be formed to expose the bonding pad 154. Additionally, a bumpprocess may further be performed to form an upper terminal 108 (e.g., asolder ball or a solder bump) connected to the bonding pad 154.

Referring to FIG. 4F, the substrate 100 may be recessed to protrude thethrough-via 120. For example, the first bottom surface 100 b of thesubstrate 100 may be recessed by an etching process using an etchant ora slurry capable of selectively removing the material (e.g., silicon)constituting the substrate 100, a CMP process, a grinding process, orany combination thereof. The recess process may be performed until asecond bottom surface 100 c is exposed. Due to the recess process, thethrough-via 120 may be exposed from the second bottom surface 100 c. Inembodiments of the inventive concept, the top surface 100 a of thesubstrate 100 may correspond to an active surface and the second bottomsurface 100 c may correspond to a non-active surface. When the firstbottom surface 100 b of the substrate 100 is recessed, the sacrificial110 may be partially etched to be recessed.

In the protruding process of the through-via 120, the through-via 120may be exposed due to a lack of an etch selectivity between thesubstrate 100 and the via-insulating layer 112 and/or a thin thicknessof the via-insulating layer 112. For example, differently from thepresent embodiment, if the sacrificial layer 110 does not exist, thevia-insulating layer 112 may be removed to expose the through-via 120due to the lack of the etch selectivity during process recessing thesubstrate 100. The exposed portion of the through-via 120 may act as acontamination or particle source, which may cause errors in subsequentprocessing operations. Alternatively, if a diameter or size S of thethrough-via 120 becomes reduced due to a tendency to shrink a device, anaspect ratio of the via-hole 101 may become greater. This may cause adecrease of the thickness and/or step coverage of the via-insulatinglayer 112, so that a removal possibility of the via-insulating layer 112may increase during the recess process of the substrate 100. However,according to the present embodiment, even though the sacrificial layer110 is partially removed by the recess process of the substrate 100, aresidual portion of the sacrificial layer 110 may prevent thethrough-via 120 from being exposed. Thus, an etch margin of thevia-insulating layer 112 may be sufficiently secured due to thesacrificial layer 110 in the protruding process of the through-via 120.

Referring to FIG. 4G, a silicon oxide layer or a silicon nitride layermay be deposited on the second bottom surface 100 c of the substrate100, thereby forming a lower insulating layer 109. The lower insulatinglayer 109 may cover the second bottom surface 100 c of the substrate 100and the sacrificial layer 110. The lower insulating layer 109, thesacrificial layer 110, and the via-insulating layer 112 may beplanarized until the through-via 120 is exposed. The planarizationprocess may be performed by an etching process, a CMP process, agrinding process, or any combination thereof. By the planarizationprocess, the tail 110 t may be removed as illustrated in FIG. 4H or thetail 110 t may not be removed as illustrated in FIG. 4I.

In some embodiments, referring to FIG. 4H, a lower terminal 118connected to the through-via 120 may be formed on the planarized lowerinsulating layer 109. Thus, it may be possible to form the semiconductordevice 1 of FIG. 1 including the electrical connection part 11 of thevia-middle structure of FIG. 2A having the through-via 120 and thevia-insulating layer 112 surrounding the sidewall of the through-via120. The planarized lower insulating layer 109 may surround a sidewallof the lower end 120 b of the through-via 120. The lower end 120 b ofthe through-via 120 may penetrate the lower insulating layer 109 and becoplanar with a bottom surface of the lower insulating layer 109. Thelower terminal 118 may be formed to have a re-interconnected pad shape.In the present embodiment, the lower terminal 118 may include a pad andthe upper terminal 108 may include a solder ball. However, the inventiveconcept is not limited thereto. In other embodiments, the upper terminal108 and the lower terminal 118 may be formed to have a solder ball shapeor a pad shape. Alternatively, the upper terminal 108 may be formed intoa pad and the lower terminal 118 may be formed into a solder ball. Afterthe integrated circuit 103 and the metal interconnection 152 aresequentially formed, the through-via 120 may be formed. Thus, it may bepossible to form the semiconductor device 1 including the electricalconnection part 12 having the via-last structure as illustrated in FIG.2B. After the through-via 120 is formed, the integrated circuit 103 andthe metal interconnection 152 may be sequentially formed. Thus, it maybe possible to form the semiconductor device 1 including the electricalconnection part 13 having the via-first structure as illustrated in FIG.2C.

In other embodiments, referring to FIG. 4I, the lower terminal 118connected to the through-via 120 may be formed on the planarized lowerinsulating layer 109. Thus, it may be possible to form the semiconductordevice 1 of FIG. 1 including the electrical connection part 11 a havingthe through-via 120, the via-insulating layer 112 surrounding thesidewall of the through-via 120, and the tail 110 t surrounding thesidewall of the lower end 120 b of the through-via 120. The electricalconnection part 11 a may be formed to have the via-middle structure likethe present embodiment. Alternatively, the electrical connection part 11a may be formed to have the via-last structure as illustrated in FIG. 2Bor the via-first structure as illustrated in FIG. 2C.

As illustrated in FIG. 4J, the via-insulating layer 112 may surround thesidewall of the lower end 120 b of the through-via 120, and a portion ofthe sacrificial layer 110, for example, the tail 110 t may furthersurround the lower end portion 120 b of the through-via 120. The tail110 t may suppress removal of the via-insulating layer 112 in a region70 adjacent to the second bottom surface 100 c of the substrate 100during the process recessing the substrate 100. Thus, the tail 110 t maysuppress exposure of the sidewall of the lower end 120 b of thethrough-via 120 adjacent to the second bottom surface 100 c of thesubstrate 100. Moreover, the tail 110 t may prevent the through-via 120from being in contact with the substrate 100. In other embodiments, thesacrificial layer 110 may be removed by the planarization process of thelower insulating layer 109. In still other embodiments, if thesacrificial layer 110 is formed after the via-insulating layer 112 isformed as illustrated in FIG. 5A, the tail 110 t may be disposed betweenthe via-insulating layer 112 and the through-via 120 and surround thelower end 120 b of the through electrode 120 as illustrated in FIG. 4K.In yet other embodiments, if the second via-insulating layer 113 isformed after the first via-insulating layer 112 and the sacrificiallayer 110 are formed as illustrated in FIG. 5B, the tail 110 t may bedisposed between the first and second via-insulating layers 112 and 113and surround the lower end 120 b of the through electrode 120 asillustrated in FIG. 4L.

<Modified Example of Fabricating Method>

FIGS. 6A to 6H are cross-sectional views illustrating a method forfabricating a semiconductor device according to other embodiments of theinventive concept. FIG. 7A and 7B are cross-sectional views illustratingprocess examples of FIG. 6B.

Referring to FIG. 6A, after the integrated circuit 103 is formed by thesame processes as or similar processes to the processes described withreference to FIGS. 4A to 4E, the through-via 120 may be formed topenetrate the substrate 100 and then the metal interconnection 152 maybe formed to connect the integrated circuit 103 and the through-via 120to each other. Before the through-via 120 is formed, the sacrificiallayer 110 may be formed to fill the lower part of the via-hole 101 by aFCVD method. The sacrificial layer 110 may include the tail 100 t ornot. In other embodiments, the via-insulating layer 112, the sacrificiallayer 110 and the through-via 120 may be sequentially formed asillustrated in FIG. 5A. In still other embodiments, the via-insulatinglayer 112, the sacrificial layer 110, the second via-insulating layer113, and the through-via 120 may be sequentially formed as illustratedin FIG. 5B.

Referring to FIG. 6B, the first bottom surface 100 b of the substrate100 may be recessed. In the present embodiment, the second bottomsurface 100 c may be formed by recessing the first bottom surface 100 b.The through-via 120 may not protrude from the second bottom surface 100c. The sacrificial layer 110 may be partially recessed by the recessprocess of the first bottom surface 100 b. The recess process may beperformed by a CMP process, an etching process, a grinding process, orany combination thereof. In the present embodiment, even through theetch selectivity between the substrate 100 and the sacrificial layer 110is not sufficient, the via-insulating layer 112 and/or the through-via120 may not be exposed. Because the sacrificial layer 110 is furtherformed under the through-via 120, the through-via 120 may not be exposedwhen the first bottom surface 100 b of the substrate 100 is recessed.Thus, the recess process may be performed by the etching process ratherthan the CMP process. As a result, it may be possible to prevent orreduce contamination or particles caused by the exposure of thethrough-via 120. Even though removing amounts according to regions ofthe substrate 100 are different from each other or depths of thevia-holes 101 are different from each other, the sacrificial layer 110may prevent the through-vias 120 from being exposed. For example, asillustrated in FIG. 7A, the removing amounts according to the regions ofthe substrate 100 may be different from each other, so that a heightdifference D of the second bottom surface 100 c may occur. In this case,at least one of the through-vias 120 may be exposed. However, accordingto embodiments of the inventive concept, the sacrificial layer 110 maycompensate for the height difference D. Thus, it may be possible toprevent the through-vias 120 from being exposed. In other embodiments,as illustrated in FIG. 7, the depth difference H of the via-holes 101may occur. In this case, at least one of the through-vias 120 may beexposed. However, according to embodiments of the inventive concept, thesacrificial layer 110 may compensate for the depth difference H suchthat it may be possible to prevent the through-vias 120 from beingexposed.

Referring to FIG. 6C, the lower insulating layer 109 may be formed onthe second bottom surface 100 c of the substrate 100 and then a mask 130may be formed on the lower insulating layer 109. A photoresist may becoated and then the photoresist may be patterned to form the mask 130.The mask 130 may include an opening pattern 130 a vertically alignedwith the via-hole 101. The opening pattern 130 a may have a width W2smaller than a width W1 of the via-hole 101.

Referring to FIG. 6D, the lower insulating layer 109, the sacrificiallayer 110, and the via-insulating layer 112 may be selectively removedby an etching process using the mask 130 as an etch mask. Thus, anopening 132 exposing the through-via 120 may be formed. A sidewall ofthe opening 132 may consist of a residual sacrificial layer 110 b. Athickness of the residual sacrificial layer 110 b and/or a width of theopening 132 may be changed according to the width W2 of the openingpattern 130 a of the mask 130.

For example, as illustrated in FIG. 6E, if the width W2 of the openingpattern 130 a is equal to or similar to a width A of the through-via120, the residual sacrificial layer 110 b may be formed to have athickness equal to or similar to the thickness of the via-insulatinglayer 112. And the opening 132 may be formed to have a width B equal toor similar to the width A of the through-via 120.

In other examples, as illustrated in FIG. 6F, if the width W2 of theopening pattern 130 a is less than the width A of the through-via 120,the residual sacrificial layer 110 b may be formed to have a thicknessgreater than the thickness of the via-insulating layer 112. And theopening 132 may be formed to have a width B less than the width A of thethrough-via 120.

In still other examples, as illustrated in FIG. 6G, if the width W2 ofthe opening pattern 130 a is greater than the width A of the through-via120, the residual sacrificial layer 110 b may be formed to have athickness less than the thickness of the via-insulating layer 112 or theresidual sacrificial layer 110 b may be removed. And the opening 132 maybe formed to have a width B greater than the width A of the through-via120. In this case, the thin thickness of the residual sacrificial layer110 b consisting of the sidewall of the opening 132 may not reliablyprevent etching damage applied to the substrate 100, and the substrate100 may be exposed through the opening 132.

In the present embodiment, the lower insulating layer 109 and thesacrificial layer 110 may be selectively removed by the etching processusing the mask 130 including the opening pattern 130 a which has thewidth W less than the width W1 of the via-hole 101 and equal to orgreater than the width A of the through-via 120. As a result, asillustrated in FIG. 6E, the residual sacrificial layer 110 b may havethe thickness equal to or similar to the thickness of the via-insulatinglayer 112, and the opening 132 may have the width B equal to or similarto the width A of the through-via 120. Or, as illustrated in FIG. 6F,the residual sacrificial layer 110 b may have the thickness greater thanthe thickness of the via-insulating layer 112, and the opening 132 mayhave the width B less than the width A of the through-via 120.

Referring to FIG. 6H, the lower terminal 118 electrically connected tothe through-via 120 may be formed on the lower insulating layer 109. Thelower terminal 118 may include an extending portion 118 e extendingalong the second bottom surface 100 c of the substrate 100 and aprotruded portion 118 p extending from the extending portion 118 e intothe opening 132. The protruded portion 118 p is connected to the lowerend 120 b of the through-via 120. The extending portion 118 e of thelower terminal 118 may be re-interconnected. The protruded portion 118 pmay be electrically insulated from the substrate 100 by the residualsacrificial layer 110 b, and the extending portion 118 e may beelectrically insulated from the substrate 100 by the lower insulatinglayer 109. In other embodiments, the lower terminal 118 may be formed tohave a solder bump shape or a solder ball shape.

The semiconductor device 1 of FIG. 1 including the electrical connectionpart 14 of the via-middle structure of FIG. 2D having the recessedthrough-via 120 may be formed through the processes described above. Inother embodiments, it may be possible to form the semiconductor device 1including the electrical connection part 12 having the via-laststructure as illustrated in FIG. 2B. Alternatively, it may be possibleto form the semiconductor device 1 including the electrical connectionpart 13 having the via-first structure as illustrated in FIG. 2C.

<Applications>

FIG. 8A is a schematic block diagram illustrating an example of memorycards including semiconductor devices according to embodiments of theinventive concept. FIG. 8B is a schematic block diagram illustrating anexample of information processing systems including semiconductordevices according to embodiments of the inventive concept.

Referring to FIG. 8A, a memory card 1200 may include a memory controller1220 that controls data communication between a host and the memorydevice 1210. An SRAM device 1221 may be used as an operation memory of acentral processing unit (CPU) 1222. A host interface unit 1223 may beconfigured to include a data communication protocol between the memorycard 1200 and the host. An error check and correction (ECC) block 1224may detect and correct errors of data, which are read out from thememory device 1210. A memory interface unit 1225 may interface with thememory device 1210. The CPU 1222 may perform overall operations for dataexchange of the memory controller 1220. The memory device 1210 mayinclude at least one of the semiconductor device 1 and the semiconductorpackage 90 according to embodiments of the inventive concept.

Referring to FIG. 8B, an information processing system 1300 may includea memory system 1310 provided with at least one of the semiconductordevice 1 and the semiconductor package 90 according to embodiments ofthe inventive concept. The information process system 1300 may include amobile device or a computer. For example, the information system 1300may include the memory system 1310, a modem 1320, a central processingunit (CPU) 1330, a RAM 1340, a user interface unit 1350. The memorysystem 1310 may include a memory device 1311 and a memory controller1312. The memory system 1310 may consist of the same elements as thememory card 1200 of FIG. 8A. The memory system 1310 may store dataprocessed by the CPU 1330 or data input from an external system. Theinformation processing system 1300 may further include a memory card, asolid state disk (SSD), and/or other application chipsets.

According to embodiments of the inventive concept, because the flowablechemical vapor deposition layer is formed under the through-via, athickness of the insulating layer of the through-via may be reinforced.Thus, it is possible to secure an etching margin of the insulating layerof the through-via during the process of protruding the through-via. Asa result, contamination or particles caused by the exposure of thethrough-via may be prevented or reduced to improve yield and electricalcharacteristics of the semiconductor device. Additionally, the flowablechemical vapor deposition layer may compensate for the height differenceof the bottom surface of the substrate and/or the depth difference ofthe via-holes, such that process errors may be prevented or minimized.

While the inventive concept has been described with reference to exampleembodiments, it will be apparent to those skilled in the art thatvarious changes and modifications may be made without departing from thespirit and scope of the inventive concept. Therefore, it should beunderstood that the above embodiments are not limiting, butillustrative. Thus, the scope of the inventive concept is to bedetermined by the broadest permissible interpretation of the followingclaims and their equivalents, and shall not be restricted or limited bythe foregoing description.

What is claimed is:
 1. A semiconductor device comprising: a substratehaving an active surface, a non-active surface, and a via-hole extendingfrom the active surface to the non-active surface; a through-viaprovided in the via-hole; a via-insulating layer extending along aninner sidewall of the via-hole and surrounding a sidewall of thethrough-via; a sacrificial layer extending along the inner sidewall ofthe via-hole from the via-insulating layer to the non-active surface ofthe substrate; a lower insulating layer covering the non-active surfaceof the substrate; and a terminal provided on the lower insulating layerand electrically connected to the through-via.
 2. The semiconductordevice of claim 1, wherein the sacrificial layer comprises a flowablechemical vapor deposition layer; and wherein the via-insulating layercomprises a non-flowable chemical vapor deposition layer.
 3. Thesemiconductor device of claim 2, wherein the through-via includes alower end that protrudes outward from the non-active surface of thesubstrate; and wherein the sacrificial layer surrounds a sidewall of thelower end of the through-via.
 4. The semiconductor device of claim 2,wherein the through-via comprises a lower end not reaching thenon-active surface of the substrate; wherein the terminal includes aprotruded portion which protrudes toward the via-hole and is connectedto the lower end of the through-via; and wherein the protruded portionis electrically insulated from the substrate by the sacrificial layer.5. The semiconductor device of 4, wherein the sacrificial layer has athickness substantially equal to that of the via-insulating layer, andwherein the protruded portion of the terminal has a width substantiallyequal to a width of the lower end of the through-via.
 6. Thesemiconductor device of claim 4, wherein the sacrificial layer has athickness greater than that of the via-insulating layer, and wherein theprotruded portion of the terminal has a width less than that of thelower end of the through-via.
 7. A method for fabricating asemiconductor device, comprising: forming a hole opened toward a topsurface of a substrate, the hole partially penetrating the substrate;forming a sacrificial layer partially filling the hole; forming athrough-via in the hole partially filled with the sacrificial layer;forming a via-insulating layer between the through-via and thesubstrate; and exposing the through-via through a bottom surface of thesubstrate, wherein forming the sacrificial layer comprises: forming aninsulating flowable layer on the substrate; and constricting theinsulating flowable layer to form a solidified flowable layer; whereinforming the via-insulating layer comprises: after forming thesacrificial layer, forming an insulating layer extending along a surfaceof the sacrificial layer and an inner sidewall of the hole.
 8. Themethod of claim 7, wherein exposing the through-via comprises: recessingthe bottom surface of the substrate to expose a lower end of thethrough-via, the lower end of the through-via being surrounded by thesacrificial layer; forming a lower insulating layer covering thesacrificial layer on the recessed bottom surface; and planarizing thelower insulating layer and the sacrificial layer to expose the lower endof the through-via.
 9. The method of claim 7, further comprising:forming a barrier metal layer between the via-insulating layer and thethrough-via.
 10. The method of claim 7, wherein forming thevia-insulating layer comprises: before forming the sacrificial layer,forming a first insulating layer extending an inner surface of the hole.11. The method of claim 10, wherein forming the via-insulating layerfurther comprises: after forming the sacrificial layer, forming a secondinsulating layer extending a surface of the sacrificial layer and aninner sidewall of the first insulating layer in the hole.
 12. The methodof claim 7, wherein forming the insulating flowable layer comprises:providing a silicon-contained compound and an oxidizing agent on thesubstrate; and condensing the silicon-contained compound and theoxidizing agent.
 13. The method of claim 12, wherein forming thesolidified flowable layer comprises: performing a plasma treatment or anannealing treatment on the insulating flowable layer to convert theinsulating flowable layer into a constricted silicon oxide layer havinga solid phase.
 14. A method for fabricating a semiconductor device,comprising: forming a hole opened toward a top surface of a substrate,the hole partially penetrating the substrate; forming a sacrificiallayer partially filling the hole; forming a through-via in the holepartially filled with the sacrificial layer; forming a via-insulatinglayer between the through-via and the substrate; and exposing thethrough-via through a bottom surface of the substrate, wherein formingthe sacrificial layer comprises: forming an insulating flowable layer onthe substrate; and constricting the insulating flowable layer to form asolidified flowable layer; wherein exposing the through-via comprises:recessing the bottom surface of the substrate to expose the sacrificiallayer without protruding the through-via; forming a lower insulatinglayer on the recessed bottom surface; and selectively removing thesacrificial layer and the via-insulating layer to expose a lower end ofthe through-via.